I. Field of the Disclosure
The technology of the disclosure relates generally to control circuits, and particularly to control circuits that generate output enable signals.
II. Background
Electronic devices, such as mobile phones and computer tablets, have become common in contemporary society for supporting various everyday uses. These electronic devices each commonly include a microphone and speakers. Typical microphones and speakers used in electronic devices have analog interfaces, requiring dedicated two (2) port wiring to connect each device. However, electronic devices may include multiple audio devices, such as multiple microphones and/or speakers. Thus, it may be desired to allow for a microprocessor or other control device in such electronic devices to be able to communicate audio data to multiple audio devices over a common communications bus. Further, it may be desired to provide a defined communications protocol for transporting digital data relating to audio channels to different audio devices in an electronic device over a common communications bus.
In this regard, the MIPI® Alliance has announced SoundWire™ as a communications protocol for transporting digital data relating to audio channels to different audio devices associated with an electronic device. In SoundWire™, one SoundWire™ master interface allows a master electronic device (“master device”), or monitor communicatively coupled thereto, to communicate over a common communications bus with one or more slave electronic devices (“slave devices”) coupled to SoundWire™ slave interfaces. As of this writing, the current version of SoundWire™ is revision 1.0, which was made internally available on Mar. 12, 2015 to MIPI® Alliance members through the MIPI® sharepoint file server.
The common communications bus in SoundWire™ includes two separate wires: a common data wire (“DATA”) and a common clock wire (“CLK”). In an attempt to provide a low power consumption environment, the SoundWire™ protocol employs a modified Non Return to Zero Inverted (“NRZI”) encoding scheme in conjunction with a double data rate (“DDR”), wherein the DATA is examined, and potentially driven, upon every transition of a clock signal on the CLK. Employing the modified NRZI encoding scheme with DDR in this manner requires that the DATA be asserted and de-asserted according to timing constraints defined in the SoundWire™ protocol. However, clock and logic circuitry used to control the DATA in this manner can be power intensive. Therefore, it would be advantageous to control the DATA so as to meet the timing constraints of the SoundWire™ protocol, while also reducing power consumption of corresponding circuitry.